The present invention relates to an inverter, and more particularly, to an inverter which is useful as a word line driver or the like in a dynamic semiconductor memory.
In recent times, the integration density and operation speed of semiconductor memories have both been greatly increased. In particular, there has been a remarkable increase in the integration density and operation speed of dynamic random-access memories (dRAMs) having memory cells each comprising one MOS transistor and one capacitor. The increase in the integration density of dRAMs has been accomplished through a reduction in the size of the elements forming the dRAM, and also through the development of novel memory-cell structures. The recent increase in the operation speed of dRAMs has been achieved through use of BICMOS circuits, each of these being a combination of a CMOS circuit and a number of bipolar transistors. BICMOS circuits are attracting considerable attention in this field, since CMOS circuits consume very little power, and because bipolar transistors operate at high speed.
FIG. 6 is a circuit diagram showing a conventional BICMOS inverter. As is shown in this figure, this inverter comprises a CMOS inverter formed of p-channel MOS transistor Qp11 and n-channel MOS transistor Qn11. The output terminal of this CMOS inverter is coupled to npn transistor T11 which functions as a buffer and is connected to output terminal Vout. Output terminal Vout can be connected to a load. Another npn transistor T12 is connected between output terminal Vout and ground terminal Vss. N-channel MOS transistor Qn12 is coupled between the collector and base of transistor T12. The gate of transistor Qn12 is connected to input terminal Vin. N-channel MOS transistor Qn13 is coupled between the base of transistor T12 and ground terminal Vss. The gate of transistor Qn13 is connected to the base of transistor T11.
When the potential at input terminal Vin is at an "H" level, the output of the CMOS inverter is at an "L" level, and transistor T11 is off. In this case, MOS transistor Qn12 is on, whereas MOS transistor Qn13 is off. Transistor T12 therefore functions as a diode. As a result, the potential at output terminal Vout is maintained at the "L" level.
When the potential at input terminal Vin is at the "L" level, the output of the CMOS inverter rises to the "H" level, and transistor T11 is turned on. As a result, MOS transistors Qn12 and Qn13 are turned off and on, respectively, and hence, transistor T12 is turned off. The potential at output terminal Vout is thereby raised to the "H" level.
The BICMOS inverter described above has bipolar transistors in the output section. Since bipolar transistors have a greater driving ability than MOS transistors, the BICMOS inverter can operate at high speed when it is used as a drive circuit for driving loads having large capacitance, and thus it can be incorporated into the peripheral circuits of a semiconductor memory. However, when the BICMOS inverter is used as the word line driver in a dRAM, a number of problems arise. One is that the BICMOS inverter cannot generate a sufficiently high "H" level output, due to the forward voltage drop V.sub.BE between the base and emitter of the bipolar transistors, as is illustrated in FIG. 7. This is because transistor T11 is inevitably turned off when the potential at output terminal Vout is equal to or higher than Vcc-V.sub.BE. When a voltage of this insufficient "H" level is applied to word line WL connected to the dRAM cell shown in FIG. 8, which consists of MOS transistor Q.sub.M and capacitor C.sub.M, the "H" level voltage applied to and held in capacitor C.sub.M is Vcc-V.sub.BE -Vth, where Vth is the threshold voltage of MOS transistor Q.sub.M. When Vcc is 5V, VBE is 0.6V, and Vth is 1.2V, the "H" level voltage will be 3.2V, which is 64% of power-supply voltage Vcc.
Another problem inherent in the BICMOS inverter described above is that its use in a semiconductor memory will work against the high integration of the memory, because of the use of bipolar transistors, which take up a large area of the circuit. In the case of, for example, a 16M bit dRAM which will be more commonly used in the future, the word lines are arranged at extremely short intervals of 2 to 3 nm. The BICMOS inverter, which comprises one CMOS circuit and several bipolar transistors, is too large to be arranged between the adjacent word lines of the 16M bit dRAM.
As has been already mentioned, when the conventional BICMOS inverter is used as the word line driver in a dRAM, a sufficiently high "H" level voltage cannot be provided, and the high integration of the dRAM will not be possible to the degree desired.